This relates generally to communications links, and more particularly, to high-speed input-output (I/O) communications links.
A typical communications link includes a transmitter (TX) module, a receiver (RX) module, and a channel that connects the TX module to the RX module. The TX module transmits a serial data bit stream across the channel to the RX module. Typical high-speed transmit data rates can be as high as 10 Gbps (gigabits per second) or more. Communications links operating at such high data rates are often referred to as high-speed serial links or high-speed I/O links.
Oftentimes, the RX module includes a decision feedback equalizer (DFE) that is used to provide equalization for analog signals which may have been degraded when being transmitted through a band limited channel (i.e., by attenuating low frequency components or boosting high frequency components). Consider a conventional decision feedback equalizer that includes an amplifier that is coupled to multiple differential pairs serving as delay taps. This type of equalizer is capable of canceling out inter-symbol interference (ISI) by summing an input signal at discrete time intervals with a weighted sum of the previously sampled values, which are being fed back as delay tap coefficients.
The differential pairs may therefore implement a current summation operation for the equalizer. The summed current is provided to a load resistance, thereby generating a summed voltage at a DFE summation node. The DFE summation node is fed to an input of a digital sampler. For proper operation of the digital sampler, a sufficiently high input common mode voltage is required. When the magnitude of the tap coefficients are large, the use of multiple differential pairs may result in a reduction in the digital sampler input common mode voltage and can substantially degrade the performance of the decision feedback equalizer.